Market
The semiconductor manufacturing process involves two distinct phases: wafer processing, commonly referred to as the “front-end” and assembly and test, commonly referred to as the “back-end”. Once the semiconductor chip (also referred to as a “die”) has been created in the front-end wafer fabrication process, Besi’s assembly equipment is used by customers to produce advanced semiconductor assemblies or “packages” incorporating a number of process steps such as (i) die sorting or “pick and place” of good versus bad dies, (ii) die bonding to leadframes, substrates, wafers and other chips to facilitate an electrical interconnection, (iii) die molding to encapsulate the assembled die and protect it from external contamination, (iv) chemical plating to provide different physical properties at various stages of the assembly process and (v) trimming and forming of leadframe carriers housing chips and/or singulation (cutting) of substrate and wafer level devices prior to their placement on a printed circuit board and ultimately, final testing.
In addition, new 2.5D, 3D and chiplet-based semiconductor device architectures used in generative AI applications now require assembly processes such as hybrid bonding and Thermo Compression Bonding (“TCB”) to be used in front-end semiconductor manufacturing.
Assembly process technologies
Semiconductor assembly involves three primary process technologies depending on the product application required. Leadframe assembly, the most traditional approach, involves the electrical connection of the chip via a wire bonding process to a metal leadframe. Substrate assembly is used most frequently in product applications that require relatively high degrees of miniaturization and chip density such as smartphones, servers, tablets and laptops as well as wireless, automotive and cloud-based internet applications. In a typical substrate assembly, no metal leadframes are utilized and the electrical connection of the chip is made directly either through (i) a wire bonding process to a multi-layer substrate or (ii) the creation of direct connections to the multi-layer substrate via a flip chip or thermo compression die bonding process.
Wafer level assembly is the most advanced and rapidly growing assembly technology and the area in which we have invested significant development resources for future growth. It is our most important area of focus today as customers seek assembly solutions for next generation generative AI applications in the areas of datacenters, PCs, tablets, servers and smartphones as well as large language learning and inferencing models and related software. Wafer level assembly involves placing single or multiple dies or chiplets onto high I/O density wafers to form integrated subsystems. In wafer level packaging, the electrical interconnections between chips are facilitated without the need for a leadframe carrier or substrate interposer. Wafer level assembly is particularly well suited for device nodes of <3 nanometers, requiring placement accuracy <1 micron.
Hybrid bonding represents the most important evolution of die to die interconnect technology in wafer level assembly. It replaces traditional reflowed flip chip solder bumps with a direct copper-to-copper connection between a chip and a wafer. Versus flip chip assembly, it facilitates significantly higher data transfer speeds and chip density while lowering energy consumption, heat dissipation and cost of ownership. Hybrid bonding also facilitates the development of 3D chip architectures as well as increased performance, features, complexity and functionality in both logic and memory applications. Further, wafer level assembly can also be achieved through a TCB chip to wafer technology, a 2.5D assembly process whereby the electrical connection is formed using solder bumps by applying heat and pressure during the bonding process. These two technologies are compatible and complementary for wafer level die bonding whose applications will vary depending on the size, accuracy, density, complexity and throughput required as well as the cost of ownership involved in production environments.
